module tb_register();
    reg [3:0] in;
    reg load, clk, reset;
    wire [3:0] q;
    register dut(in, load, q, clk, reset);
    always
    begin
        clk = 1; #5; clk = 0; #5;
    end
    initial
    begin
        $dumpfile("tb_register");
        $dumpvars;
        reset=1; in=4'b1100;load = 0;#10;
        load=1; #10;
        load=0;reset = 0; in=4'b0100;#30;
        load=1;#30;
        $finish;
    end
endmodule